The 17th Workshop on Design and Architectures for Signal and Image Processing (DASIP 2024) will take place in conjunction with the
HiPEAC 2024 conference in Munich, Germany, January 17 - 19, 2024.
Abstract registration: October 20October 27, 2023 (EXTENDED)
Paper submission: October 27November 12, 2023 (EXTENDED, FINAL)
Notification of acceptance: December 1December 8, 2023
Camera ready submission: December 11December 18, 2023
All deadlines are in Anywhere on Earth (AoE)
Machine learning and deep learning architectures for inference and training
Systems for autonomous vehicles: cars, drones, ships and space applications
Image processing and compression architectures
Smart cameras, security systems, behaviour recognition
Edge and cloud processing: special routing, configurable co-processors and low energy considerations
Real-time cryptography, secure computing, financial and personal data processing
Computer arithmetic, approximate computing, probabilistic computing, nanocomputing, bio-inspired computing
Biological data collection and analysis, bioinformatics
Personal digital assistants, natural language processing, wearable computing and implantable devices
Global navigation satellite and inertial navigation systems
Design verification and fault tolerance
Embedded system security and security validation
System-level design and hardware/software co-design
High-level synthesis, logic synthesis, communication synthesis
Embedded real-time systems and real-time operating systems
Rapid system prototyping, performance analysis and estimation
Formal models, transformations, algorithm transformations and metrics
Embedded platforms for multimedia and telecommunication
Many-core and multi-processor systems, SoCs, and NoCs
Reconfigurable ASIPs, FPGAs, and dynamically reconfigurable systems
Memory system and cache management
Asynchronous (self-timed) circuits and analog and mixed-signal circuits
The best paper award of DASIP 2024 has been granted to Chilankamol Sunny (Indian Institute of Technology Palakkad), Satyajit Das (Indian Institute of Technology Palakkad), Kevin Martin (Lab-STICC - Université de Bretagne-Sud), and Philippe Coussy (Lab-STICC - Université de Bretagne-Sud) for their paper entitled Standalone Nested Loop Acceleration on CGRAs for Signal Processing Applications.
Congratulations!
Tiago M. Dias
ISEL - IPL / INESC-ID, Lisbon, Portugal
tiago.dias@isel.pt
Paola Busia
Università degli Studi di Cagliari, Cagliari, Italy
paola.busia@unica.it
Alfonso Rodríguez
Universidad Politécnica de Madrid, Madrid, Spain
Andrea Pinna
Sorbonne University, Paris, France
Diana Goehringer
TU Dresden, Dresden, Germany
Jean-Pierre David
Ecole Polytechnique de Montreal, Montreal, Canada
João M. P. Cardoso
University of Porto, Porto, Portugal
Karol Desnos
INSA Rennes - IETR laboratory, Rennes, France
Marek Gorgoń
AGH University of Science and Technology, Kraków, Poland
Michael Huebner
Brandenburg University of Technology, Cottbus-Senftenberg, Germany
Miguel Chavarrías
Universidad Politécnica de Madrid, Madrid, Spain
Paolo Meloni
University of Cagliari, Cagliari, Italy
Pierre Langlois
Ecole Polytechnique de Montreal, Montreal, Canada
Sebastien Pillement
University of Nantes - IETR, Nantes, France
Sergio Petruz
TU Dresden, Dresden, Germany
Tomasz Kryjak
AGH University of Science and Technology, Kraków, Poland
Andrea Pinna
Sorbonne Univeristy, France
Andrés Otero
Universidad Politécnica de Madrid, Spain
Arnaldo Oliveira
Universidade de Aveiro - DETI / Instituto de Telecomunicações, Portugal
Bertrand Granado
Sorbonne Université, France
Christian Pilato
Politecnico di Milano, Italy
Christopher Claus
Robert Bosch GmbH,
Daniel Chillet
IRISA/ENSSAT University of Rennes 1, France
Diana Goehringer
TU Dresden, Germany
Dimitrios Soudris
National Technical University of Athens, Greece
Eduardo de La Torre
Universidad Politécnica de Madrid, Spain
Francesca Palumbo
Information Eng. Unit - PolComIng - University of Sassari, Italy
Frank Hannig
Friedrich-Alexander University Erlangen-Nürnberg, Germany
Gabriel Caffarena
University CEU San Pablo, Spain
Gustavo Marrero Callico
Universidad de Las Palmas de Gran Canaria, Spain
Guy Gogniat
Université de Bretagne Sud - UEB, France
Jean Francois Nezan
INSA Rennes, IETR laboratory, France
Jean Pierre David
Ecole Polytechnique de Montréal,
Joao Cardoso
University of Porto, Portugal
João Canas Ferreira
University of Porto, Portugal
Jorge Portilla
Universidad Politécnica de Madrid, Spain
Kevin J. M. Martin
Lab-STICC - Université de Bretagne-Sud,
Marek Gorgon
AGH University of Science and Technology, Poland
Martin Danek
Daiteq s.r.o., Czechia
Mateusz Komorkiewicz
IEEE, Poland
Maxime Pelcat
IETR/INSA, France
Milos Drutarovsky
Technical University of Kosice, Slovak Republic
Nuno Roma
Universidade de Lisboa, Portugal
Olivier Romain
University of Cergy Pontoise, France
Oscar Gustafsson
Linköping University, Sweden
Paolo Meloni
University of Cagliari, Italy
Ruben Salvador
CentraleSupélec - IETR, France
Sebastien Pillement
University of Nantes - IETR, France
Tomasz Kryjak
AGH University of Science and Technology, Poland
Yannick Le Moullec
Tallinn University of Technology, Estonia
In conjunction with the 18th HiPEAC Conference
Toulouse, France
January 16-18
Website
In conjunction with the 17th HiPEAC Conference
Budapest, Hungary
June 20-22
Website
In conjunction with the 16th HiPEAC Conference
Virtual Conference, Online
January 18-20
Website
Polytechnique Montréal, Canada
October 16-18
Website
University of Porto, Portugal
October 10-12
Website
Technical University of Dresden, Germany
September 27-29
RISA/INRIA Rennes, France
October 12-14
AGH University of Science and Technology, Poland
September 23-25
Technical University of Madrid, Spain
October 8-10
University of Cagliari, Italy
October 8-10
Karlsruhe Institute of Technology, Germany
October 23-25
Tampere University of Technology, Finland
November 2-4
University of Edinburgh, UK
October 26-28
Sophia Antipolis, France
September 22-24
Brussels, Belgium
November 24
Grenoble, France
November 27-29