DASIP 2024: Workshop on Design and Architectures for Signal and Image Processing
In conjunction with the HiPEAC 2024 Conference in Munich, Germany, January 17-19, 2024
CALL FOR PAPERS WORKSHOP PROGRAM

About DASIP

The Workshop on Design and Architectures for Signal and Image Processing (DASIP) provides an inspiring international forum for the latest innovations and developments in the field of leading signal, image and video processing and machine learning in custom embedded, edge and cloud computing architectures and systems.

The workshop program will include keynote speeches and contributed paper sessions.

The DASIP 2024 proceedings will be published in the Springer LNCS Series and made available on the Springer Link website.

 

Venue

The 17th Workshop on Design and Architectures for Signal and Image Processing (DASIP 2024) will take place in conjunction with the
HiPEAC 2024 conference in Munich, Germany, January 17 - 19, 2024.

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Importante Dates

Abstract registration: October 20October 27, 2023 (EXTENDED)
Paper submission: October 27November 12, 2023 (EXTENDED, FINAL)
Notification of acceptance: December 1December 8, 2023
Camera ready submission: December 11December 18, 2023

All deadlines are in Anywhere on Earth (AoE)

Call for Papers

Prospective authors are invited to submit manuscripts on the following topics, but not limited to them.

Custom embedded, edge and cloud architectures and systems

Machine learning and deep learning architectures for inference and training
Systems for autonomous vehicles: cars, drones, ships and space applications
Image processing and compression architectures
Smart cameras, security systems, behaviour recognition
Edge and cloud processing: special routing, configurable co-processors and low energy considerations
Real-time cryptography, secure computing, financial and personal data processing
Computer arithmetic, approximate computing, probabilistic computing, nanocomputing, bio-inspired computing
Biological data collection and analysis, bioinformatics
Personal digital assistants, natural language processing, wearable computing and implantable devices
Global navigation satellite and inertial navigation systems

Design Methods and Tools

Design verification and fault tolerance
Embedded system security and security validation
System-level design and hardware/software co-design
High-level synthesis, logic synthesis, communication synthesis
Embedded real-time systems and real-time operating systems
Rapid system prototyping, performance analysis and estimation
Formal models, transformations, algorithm transformations and metrics

Development Platforms, Architectures and Technologies

Embedded platforms for multimedia and telecommunication
Many-core and multi-processor systems, SoCs, and NoCs
Reconfigurable ASIPs, FPGAs, and dynamically reconfigurable systems
Memory system and cache management
Asynchronous (self-timed) circuits and analog and mixed-signal circuits

Authors Information

Submission Guidelines

Authors should prepare their full papers (up to 12 pages) and/or short papers (up to 6 pages, intended for work-in-progress with promising results and/or students at the early stages of their research) in the single-column Springer LNCS format. The Instructions for Proceedings Authors and the Spinger LNCS template in various formats are available through the following link:
https://www.springer.com/gp/computer-science/lncs/conference-proceedings-guidelines
The Springer’s proceedings LaTeX templates are also available in Overleaf.

Submitted papers are required to describe original unpublished work and must not be under consideration for publication elsewhere. Submissions must be fully anonymous, but authors should not hide previous work, instead, they need to make self-references in the third person.

Each submission will receive at least three independent double blind reviews from the members of the scientific committee. Authors are encouraged to take the reviewers’ comments into account when preparing the final versions of their papers and present the research during the workshop.

All accepted papers must be presented by one of the authors in order to be included in the workshop proceedings.

Paper Submission

The submission of papers is done via EasyChair. Please submit your paper through the following link:
https://easychair.org/conferences/?conf=dasip2024.

Registration

DASIP 2024 is a HiPEAC-based workshop. Hence, a registration at HiPEAC is required.

Please be aware that for each accepted paper, at least, one of the authors must pay the full registration fee in order for the paper to be included in the workshop proceedings and scheduled in the program.

Workshop

Program

Keynote Speakers

David González-Arjona

GMV

Presentations

Orbiting the Edge and Stars: Bridging the gap between Space Avionics and Edge Computing, challenges and space mission's needs

by David González-Arjona

A highly configurable platform for advanced PPG analysis

by Flavie Durand De Gevigney

sEMG-based Gesture Recognition with Spiking Neural Networks on Low-power FPGA

by Matteo Antonio Scrugli

Scalable FPGA Implementation of Dynamic Programming for Optimal Control of Hybrid Electrical Vehicles

by Frans Skarman

Wordlength Optimization for Custom Floating-point Systems

by Quentin Milot

An Initial Framework for Prototyping Radio-Interferometric Imaging Pipelines

by Sunrise Wang

Scratchy: A Class of Adaptable Architectures with Software-Managed Communication For Edge Streaming Applications

by Maxime Pelcat

Standalone Nested Loop Acceleration on CGRAs for Signal Processing Applications

by Chilankamol Sunny

Improving the Energy Efficiency of CNN Inference on FPGA using Partial Reconfiguration

by Zhuoer Li

Optimising Graph Representation for Hardware Implementation of Graph Convolutional Networks for Event-based Vision

by Kamil Jeziorek

Best Paper Award

The best paper award of DASIP 2024 has been granted to Chilankamol Sunny (Indian Institute of Technology Palakkad), Satyajit Das (Indian Institute of Technology Palakkad), Kevin Martin (Lab-STICC - Université de Bretagne-Sud), and Philippe Coussy (Lab-STICC - Université de Bretagne-Sud) for their paper entitled Standalone Nested Loop Acceleration on CGRAs for Signal Processing Applications.
Congratulations!

 
 

Photo Gallery

 

Committees

Chairs

Tiago M. Dias
ISEL - IPL / INESC-ID, Lisbon, Portugal
tiago.dias@isel.pt

Paola Busia
Università degli Studi di Cagliari, Cagliari, Italy
paola.busia@unica.it

Steering Committee

Alfonso Rodríguez
Universidad Politécnica de Madrid, Madrid, Spain

Andrea Pinna
Sorbonne University, Paris, France

Diana Goehringer
TU Dresden, Dresden, Germany

Jean-Pierre David
Ecole Polytechnique de Montreal, Montreal, Canada

João M. P. Cardoso
University of Porto, Porto, Portugal

Karol Desnos
INSA Rennes - IETR laboratory, Rennes, France

Marek Gorgoń
AGH University of Science and Technology, Kraków, Poland

Michael Huebner
Brandenburg University of Technology, Cottbus-Senftenberg, Germany

Miguel Chavarrías
Universidad Politécnica de Madrid, Madrid, Spain

Paolo Meloni
University of Cagliari, Cagliari, Italy

Pierre Langlois
Ecole Polytechnique de Montreal, Montreal, Canada

Sebastien Pillement
University of Nantes - IETR, Nantes, France

Sergio Petruz
TU Dresden, Dresden, Germany

Tomasz Kryjak
AGH University of Science and Technology, Kraków, Poland

Technical Program Committee

Andrea Pinna
Sorbonne Univeristy, France

Andrés Otero
Universidad Politécnica de Madrid, Spain

Arnaldo Oliveira
Universidade de Aveiro - DETI / Instituto de Telecomunicações, Portugal

Bertrand Granado
Sorbonne Université, France

Christian Pilato
Politecnico di Milano, Italy

Christopher Claus
Robert Bosch GmbH,

Daniel Chillet
IRISA/ENSSAT University of Rennes 1, France

Diana Goehringer
TU Dresden, Germany

Dimitrios Soudris
National Technical University of Athens, Greece

Eduardo de La Torre
Universidad Politécnica de Madrid, Spain

Francesca Palumbo
Information Eng. Unit - PolComIng - University of Sassari, Italy

Frank Hannig
Friedrich-Alexander University Erlangen-Nürnberg, Germany

Gabriel Caffarena
University CEU San Pablo, Spain

Gustavo Marrero Callico
Universidad de Las Palmas de Gran Canaria, Spain

Guy Gogniat
Université de Bretagne Sud - UEB, France

Jean Francois Nezan
INSA Rennes, IETR laboratory, France

Jean Pierre David
Ecole Polytechnique de Montréal,

Joao Cardoso
University of Porto, Portugal

João Canas Ferreira
University of Porto, Portugal

Jorge Portilla
Universidad Politécnica de Madrid, Spain

Kevin J. M. Martin
Lab-STICC - Université de Bretagne-Sud,

Marek Gorgon
AGH University of Science and Technology, Poland

Martin Danek
Daiteq s.r.o., Czechia

Mateusz Komorkiewicz
IEEE, Poland

Maxime Pelcat
IETR/INSA, France

Milos Drutarovsky
Technical University of Kosice, Slovak Republic

Nuno Roma
Universidade de Lisboa, Portugal

Olivier Romain
University of Cergy Pontoise, France

Oscar Gustafsson
Linköping University, Sweden

Paolo Meloni
University of Cagliari, Italy

Ruben Salvador
CentraleSupélec - IETR, France

Sebastien Pillement
University of Nantes - IETR, France

Tomasz Kryjak
AGH University of Science and Technology, Poland

Yannick Le Moullec
Tallinn University of Technology, Estonia

Prior Editions

DASIP is a long-running annual workshop open to the presentation and discussion of the latest innovations and developments in the field of leading signal, image and video processing and machine learning in custom embedded, edge and cloud computing architectures and systems.

It was organized for the first time in 2007 in Grenoble, France, and since then it has alternated between several countries in Europe and Canada. The last four editions were co-located with HiPEAC.

  • DASIP 2023

    In conjunction with the 18th HiPEAC Conference
    Toulouse, France
    January 16-18
    Website

  • DASIP 2022

    In conjunction with the 17th HiPEAC Conference
    Budapest, Hungary
    June 20-22
    Website

  • DASIP 2021

    In conjunction with the 16th HiPEAC Conference
    Virtual Conference, Online
    January 18-20
    Website

  • DASIP 2019

    Polytechnique Montréal, Canada
    October 16-18
    Website

  • DASIP 2018

    University of Porto, Portugal
    October 10-12
    Website

  • DASIP 2017

    Technical University of Dresden, Germany
    September 27-29

  • DASIP 2016

    RISA/INRIA Rennes, France
    October 12-14

  • DASIP 2015

    AGH University of Science and Technology, Poland
    September 23-25

  • DASIP 2014

    Technical University of Madrid, Spain
    October 8-10

  • DASIP 2013

    University of Cagliari, Italy
    October 8-10

  • DASIP 2012

    Karlsruhe Institute of Technology, Germany
    October 23-25

  • DASIP 2011

    Tampere University of Technology, Finland
    November 2-4

  • DASIP 2010

    University of Edinburgh, UK
    October 26-28

  • DASIP 2009

    Sophia Antipolis, France
    September 22-24

  • DASIP 2008

    Brussels, Belgium
    November 24

  • DASIP 2007

    Grenoble, France
    November 27-29

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